The present invention relates to the placement and routing of electronic circuit designs for integrated circuits, and, more specifically, to an improved port assignment in hierarchical integrated circuit designs by abstracting macro logic.
In a hierarchical design approach, the logic of an integrated circuit (“IC”) or chip is partitioned into smaller portions that are assigned to predefined areas of the chip. These smaller design portions (which may comprise area, logic, interconnects and timing assertions) are typically referred to as macros. Usually, some logic will not be assigned to any macro. This logic is considered as being on the top level of the hierarchy. It may well be that the hierarchy is nested and a chip is partitioned into one or more units and each unit is partitioned into one or more macros. The top level is typically referred to as a “unit” and the lower level(s) as “macros”.
A port of a macro is the point (or small area) at which the internal and external signals are connected to each other. Port assignment of macros is in general important for the quality of the resulting layout. A relatively good port assignment may be achieved if a flat placement step optimizing netlength, congestion and/or timing that restrict the logic assigned to each macro to the designated area is followed by a detailed routing step. The ports are then the points where the external net enters the area assigned to the macro logic. This optimization considers global as well as local information.
However this approach has to deal with the entire complexity of the unit and thus comprises relatively considerable effort in run time and memory, contrary to the “divide and conquer” concept of hierarchy. Typically the vast majority of nets and circuits are inside the macros. Another problem is that in the early phases of the design process the internal logic of macros may not be designed yet. There may only be some guidelines in existence as to which ports are to be close to each other.